This invention relates to communication systems and more specifically to a system and method in which a receiver of an integrated circuit has a peaking function that is adjustable by varying one or more programming signal inputs to the receiver.
Data communication systems face many challenges today. The sizes of integrated circuit are being reduced rapidly, and data transmission speeds are increasing, requiring decreases in operating voltages and current levels, while signal losses increase over transmission media, and higher noise appears. The challenges are especially great in high speed serial data communications where high data transfer rates are required in difficult environments in which signals are highly attenuated over the communication channel and much noise is present due to cross-coupled interference (“cross-talk”) among others. In addition, a transmitter or a receiver, as designed, may need to be capable of transmitting, or receiving, communications at multiple different transmission rates, depending on customer needs.
The maximum transmission rate and distance that data can be transmitted within a given communication system including a transmitter, transmission medium, and receiver are limited by jitter. Jitter is the tendency of data signal transitions to occur at different times during respective signal periods. While data signal receivers generally receive signals by sampling the input signal at the center of the period of an active signal at a time halfway between up and down signal transitions or halfway between down and up signal transitions, jitter introduces uncertainty to that determination, such that occasionally a data transition can occur at the time that coincides with the time that the input signal is sampled, thus causing the input signal to be sampled incorrectly. When a high amount of jitter is present, high data rate signals cannot be received reliably to keep bit error rates within tolerable limits. Jitter arises from a communication system in the following ways, among others. Jitter arises because insertion loss (i.e. the attenuation of a transmitted signal over a transmission medium) increases with frequency, causing signals to take longer to transition between levels, making it more difficult to receive higher frequency signals. Jitter also arises from attenuation which is due to signal reflection at one or both ends of the transmission medium, such as may arise from impedance mismatch between transmitter and transmission medium, or between receiver and transmission medium. Jitter may also be caused by inadequate control over the impedances of the transmitter and receiver, such as may arise from the impedance of an integrated circuit package.
In addition, jitter arises from signal attenuation due to inter-symbol interference (ISI), when irregular data patterns occur. Inter-symbol interference is best explained with reference to an example. Assume that a signal indicating a string of ‘1’s, e.g., a continuously high voltage level for the duration of the ‘1’s, is transmitted along a transmission medium. If within the string of all ‘1’s a single ‘0’ is transmitted, the amplitude of the single ‘0’ is highly attenuated relative to the amplitude of the ‘1’s, due to inter-symbol interference. The same is also true when a signal indicating a string of ‘0’s, e.g., a continuously low voltage level for the duration of the ‘0’s, is transmitted. If within the string of all ‘0’s a single ‘1’ is transmitted, the amplitude of the single ‘1’ is attenuated due to inter-symbol interference.
Although many prior approaches have been used to help overcome signal integrity problems, each such approach is deficient in one way or another. Prior approaches are now presented, together with their deficiencies. One approach that has been used before to relieve high insertion loss of a signal over a transmission medium has been to increase the drive strength of the transmitter that drives the signal. For this purpose, transmitters can be provided with selectable current supply levels. A higher current supply to a transmitter increases its drive strength. Thus, with this approach a transmitter is operated with a higher selected current supply when it drives a longer, or more lossy transmission line. A serious drawback to this approach, which limits its ability to be utilized, concerns cross-coupled interference. The drive strength of the transmitter is limited to a level above which cross-coupled interference to closely situated devices becomes intolerable. Thus, the transmitter drive strength cannot be arbitrarily increased.
Another approach that has been used before to relieve frequency dependent signal attenuation, i.e. high frequency rolloff, which can contribute to ISI and jitter, has been to provide pre-emphasis in a transmitter by use of an equalizer. An equalizer allows the amplitude of specific frequencies or frequency ranges of a signal spectrum to be increased or reduced relative to each other, to provide pre-emphasis in a transmitter. An equalizer typically operates by convolving the signal, in either time or frequency domain, with a transfer function having adjustable coefficients. By selecting appropriate coefficients for performing pre-emphasis at the transmitter, high frequency rolloff of the transmitted signal at the receiving end, including ISI effects, can be counteracted. In digital communications, equalizers can take the form of a finite impulse response (FIR) filter. A FIR filter includes several shift registers, with each shift register containing information for the present data bit and other preceding and/or following data bits in the bit stream representing the signal. A transfer function is implemented through multiplication or convolution of the bit stream, including the present data bit and the preceding and/or following data bits, with the set of coefficients. For example, a transfer function of a FIR filter in the z domain, can be such as H(z)=S [1+b1(z−1)+b2(z−2)+b3(z−3)], where b1, b2 and b3 are the coefficients which are stored in registers of the FIR, and S is a scaling factor. The coefficients are all negative, in order to provide pre-emphasis. The factors in determining values of the coefficients include the characteristics of the transmission medium, the speed of transmission, the type of board connect and package, etc. all of which play a role in determining the losses expected to be encountered.
Another way to implement pre-emphasis in a transmitter is described in U.S. Pat. No. 5,857,001 to Preuss. As described in that patent, a transmitter block includes an equalizer which functions to increase signal amplitude at signal transitions, with the increased signal amplitude at the transition decreasing with time thereafter with an exponential tail. While an approach such as that described in that patent can offset signal attenuation due to ISI in a transmission line, there are several significant drawbacks. For one, the driver is bulky, consuming much circuit area, and also consumes much power. In addition, the equalization is neither adjustable nor tunable, such that over or under-equalization at the transmitter end can actually cause jitter at the receiver end to exceed threshold. Another problem of performing equalization at the transmitter end is that it may not always solve problems that appear at the receiver end. This is because transmitter and receiver are manufactured on different chips provided by different vendors, such that a given receiver may or may not be connected to a transmitter that performs pre-emphasis. Therefore, it would be desirable to provide equalization in the receiver. In that way, the receiver can perform equalization of the incoming signal, regardless of the characteristics of the transmitter from which it receives the signal.
Equalization in the digital domain has been proposed for a receiver in U.S. Pat. No. 5,068,873 to Murakami. As described in that patent, a receiver is provided with a FIR type equalizer by which decisions are made at least partly based on feedback to the equalizer. During a calibration process, a sequence of test signals are processed through feed-forward and feed-backward FIR filters using a first algorithm having a fast convergence speed. Such is generally sufficient to tune the receiver to compensate for ISI over the transmission medium. By the end of the calibration process, a set of coefficients for the FIR filters is determined which provide good equalization for the transmitted signal. During normal operation, the receiver continuously tracks and monitors the transmission channel and variations in the chip temperature, and updates the coefficients in taps of the FIR through a second process, which operates somewhat more slowly. The disadvantages of using a FIR type equalizer are complicated design and operation, and high power overhead, i.e. the amount of power used to implement the FIR, as opposed to the power going into the received signal.
Yet another approach to compensating for frequency dependent signal losses at the receiver end originated conceptually in tuned peaking amplifiers developed during early television receiver research. Details of one such tuned peaking amplifier is described in The Design of CMOS Radio-Frequency Integrated Circuits, Thomas A. Lee (Cambridge University Press, Cambridge, UK, 1998), pp. 179-187. In a tuned peaking amplifier, the amplifier's gain is tuned by control over resistive, capacitive, and inductive elements at the time of design, such that an essentially flat frequency response is obtained over a relatively narrow frequency range of interest, while gain outside the frequency range of interest is allowed to be much lower. Tuned peaking amplifiers are used extensively in radio frequency (RF) wireless communications to provide selective amplification over narrow frequency bands of interest. Advantages of such amplifier designs include low power consumption, and low weight, making them attractive for use in portable RF devices.
The low power consumption and low weight of tuned peaking amplifiers also make them attractive for use as equalized receivers in high speed serial communications such as SerDes cores. SerDes cores are high speed serializer and deserializer blocks of an integrated circuit that provide high speed serial communication over relatively short links (generally less than 10 meters), such as for inter-system communication. However, the tuned peaking amplifier designs described above cannot be readily used in SerDes cores. This is because particular tuned receivers of the same SerDes core may each aim to receive different data rate signals, as determined by customer requirements. In such case, multiple different designs of tuned peaking amplifiers would have to be provided on the same SerDes core to provide this function. As SerDes cores form parts of chips including ASICs that can be installed in several different chip packages, each tuned receiver design may need further tuning for the chip to be installed a particular chip package. The tuned peaking amplifiers described above cannot be tuned after the time of design.
Therefore, it would be desirable to provide a tuned peaking amplifier for use as an equalized receiver, in which the sensitivity of the receiver over a particular frequency range of interest can be tuned by varying programming signal input to the receiver after the time of design.